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SEMICONDUCTOR DIE PACKAGE INCLUDING STAND OFF STRUCTURESCM Patents

Índice de la ficha

Updated at
24/07/2026
Numero publicacion
WO.2009032537.A1
Fecha publicacion
12/03/2009
Numero solicitud
WO2008US73841
Fecha presentacion
21/08/2008

En detalle

Resumen

A semiconductor die package. It includes a semiconductor die including a first surface and a second surface opposite the first surface, an optional conductive structure, and a leadframe structure. The leadframe structure comprises a central portion suitable for supporting the semiconductor die, and a plurality of stand-off structures coupled to the central portion of the leadframe structure. The stand-off structures can support the conductive structure, and the conductive structure is attached to the second surface of the semiconductor die.

Reivindicaciones

WHAT IS CLAIMED IS: L A leadframe structure comprising: a central portion suitable for supporting a semiconductor die comprising a first surface and a second surface opposite the first surface; and a plurality of stand-off structures coupled to or spaced from the central portion. 2. The leadframe structure of claim 1 wherein the stand-off structures are suitable for supporting a premolded clip structure, wherein the premolded clip structure is capable of being attached to the second surface of the semiconductor die. 3. The leadframe structure of claim 1 wherein the leadframe structure comprises copper. 4. The leadframe structure of claim 1 wherein the plurality of stand-off structures comprises at least four stand-off structures, wherein there is at least one stand-off structure extending from each edge of the central portion. 5. The leadframe structure of claim 1 wherein the central portion is a drain pad. 6. The leadframe structure of claim 5 further comprising a gate lead and a source lead spaced from the central portion. 7. A method comprising: stamping a metal sheet to form the leadframe structure of claim 1. 8. A semiconductor die package comprising: a semiconductor die comprising a first surface and a second surface opposite the first surface; and a leadframe structure comprising a central portion suitable for supporting the semiconductor die, and a plurality of stand-off structures coupled to the central portion of the leadframe structure, wherein the stand-off structures are capable of maintaining planarity with respect to a conductive structure comprising a planar surface. 9. The semiconductor die package of claim 8 wherein the conductive structure is a premolded clip structure, and wherein the stand-off structures are coupled to the central portion by being integral with the central portion. 10. The semiconductor die package of claim 8 wherein the semiconductor die comprises a source region and a gate region at the first surface and a drain region at the second surface, and wherein the conductive structure is a printed circuit substrate. 11. The semiconductor die package of claim 8 further comprising a molding material covering at least a portion of the leadframe structure, wherein the molding material exposes the second surface of the semiconductor die. 12. The semiconductor die package of claim 8 wherein the plurality of stand-off structures comprises at least four stand-off structures, wherein there is at least one stand-off structure extending from each edge of the central portion 13. The semiconductor die package of claim 8 further comprising a conductive adhesive between the conductive structure and the semiconductor die. 14. The semiconductor die package of claim 13 wherein the conductive adhesive comprises solder. 15. A method for forming a semiconductor die package, the method comprising: obtaining a semiconductor die comprising a first surface and a second surface opposite the first surface; obtaining a leadframe structure comprising a central portion surface suitable for supporting the semiconductor die, and a plurality of stand-off structures; and attaching the leadframe structure to the semiconductor die. 16. The method of claim 15 wherein the semiconductor die comprises a source region and a gate region at the first surface and a drain region at the second surface. 17. The method of claim 15, further comprising, attaching a conductive structure to the stand-off structures and to the semiconductor die. 18. The method of claim 17 wherein attaching the conductive structure to the semiconductor die comprises using a conductive adhesive to attach the conductive structure and the semiconductor die. 19. The method of claim 15 wherein the stand-off structures are integral with the central portion. 20. The method of claim 15 further comprising molding a molding material around at least a portion of the semiconductor die and at least a portion of the leadframe structure.

Etiquetas

Inventores
Quinones Maria Clemens yCruz Erwin VictorGestole MarvinMadrid Ruben PTangpuz Connie N
Solicitantes
Fairchild SemiconductorQuinones Maria Clemens yCruz Erwin VictorGestole MarvinMadrid Ruben PTangpuz Connie N
Clasificacion ipc
G05D 7/ 00 A IH01L 29/ 78 A IH10W 70/ 40 A I
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