Resumen
Method of manufacturing substrates (1) of integrated circuits based on cmos technology comprising: - a first step of depositing a layer of insulating material (3) on at least one support (2, 6), - a second stage of modeling the layer of insulating material giving rise to at least one pit (4) in said insulating layer (3), - a third stage of depositing a semiconductor layer (5) on the pits (4) obtained in the previous stage, so that the semiconductor material fills the pits (4) completely, - a fourth stage of mechanical-chemical planarization (cmp) that removes the semiconductor layer (5), deposited in the second stage, up to the level of the upper edge of the insulating layer (3), giving rise to a substrate (1) that allows the manufacture of integrated circuits based on three-dimensional interconnected cmos technology. (Machine-translation by Google Translate, not legally binding)