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Semiconductor leadframe for staggered board attachCM Patents

Índice de la ficha

Updated at
24/07/2026
Numero publicacion
US.2002089042.A1
Fecha publicacion
11/07/2002
Numero solicitud
US20010990846
Fecha presentacion
21/11/2001

En detalle

Resumen

The semiconductor integrated circuit device comprises a planar leadframe having lead segments arranged in alternating order into first and second pluralities, the segments having their inner tips near the chip mount pad and their outer tips remote from the mount pad. The outer tips have a solderable surface. All outer tips are bent away from the leadframe plane into the direction towards the intended attachment locations on an outside substrate such that the first segment plurality forms an angle of about 70±1° from the plane and the second segment plurality forms an angle of about 75±1° (see <cross-reference target="DRAWINGS">FIG. 4</cross-reference>). Consequently, the outer tips create a staggered lead pattern suitable for solder attachment to an outside substrate.

Etiquetas

Inventores
Madrid Ruben P
Solicitantes
Texas Instruments IncMadrid Ruben PTexas Instruments Incorporated
Clasificacion ipc
H01L 21/ 48 A IH10W 70/ 40 A I
Clasificacion cpc
257/666257/667257/672257/E23.04829/827438/111438/112257/670257/674257/676
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