Reivindicaciones
CLAIMS 1. A method of driving an antiferroelectric liquid crystal display device which has an array of addressable pixels, each of which is defined between a pair of electrodes, the method comprising the steps of applying the following sequence of monopolar voltage pulses to at least one of the pair of electrodes which define at least one selected pixel : (a) a first selection pulse operable to drive the selected pixel to a first activated state; (b) a first bias pulse operable to cause the selected pixel to attain a predetermined grey scale level ; (c) a first erasure pulse of opposite polarity to that of the first selection pulse operable to erase the memory of selected pixel and to switch the pixel to a relaxed inactive state : (d) a reset pulse operable to allow the pixel to reset in the relaxed state : (e) a second selection pulse of opposite polarity to that of the first selection pulse operable to switch the selected pixel to a second activated state ; (f) a second bias pulse operable to cause the selected pixel to attain a predetermined grey scale level ; (g) a second erasure pulse of opposite polarity to that of the second selection pulse operable to cause the selected pixel to switch to the relaxed inactive state and erase the memory of the pixel : and, (h) a reset pulse operable to allow the pixel to reset in the relaxed state. 2. A method according to claim 1 wherein the first and second bias pulse is of the same polarity as, but lower voltage than. respectively, the first and second selection pulses. 3. 3. A method according to claim 1 wherein the first and second bias pulse is of the same polarity as, but higher voltage than, respectively, the first and second selection pulses 4. 4. A method according to any one of the preceding claims, wherein the reset pulses are at zero volts. 5. A method according to any one of the preceding claims, wherein data for the selected pixel is incorporated with the first and second selection pulses. 6. A method according to any one of the preceding claims wherein data for selected pixels are incorporated with the first and second bias pulses. 7. A method according to any one of claims 1 to 5 wherein data for non-selected pixels are incorporated with the bias pulses. 8. 8. A method according to any one of the preceding claims wherein data for non-selected pixels are incorporated with the reset pulses. 9. 9. A method according to any one of the preceding claims, wherein the display device is a passive matrix display device, and one of the electrodes of each pair of electrodes is constituted by one electrode of a first array of electrodes, and the other electrode of each pair is constituted either by an electrode common to all pairs of electrodes, or one electrode of a second array of electrodes, and the said pulses are applied sequentially to selected electrodes. 10. 10. A method according to claim 8 wherein a first electrode of the pair of electrodes is maintained at a predetermined datum voltage level relative to the second electrode of the respective pair of electrodes, and the selection pulses, bias pulses, and erasure pulses are applied to the second electrode of the pair of electrodes.. 11. A method according to claim 8, wherein the selection pulses and the bias pulses are applied to a first electrode of the pair of electrodes. 12. A method according to any one of claims 1 to 7 wherein the display device comprises an antiferroelectric liquid crystal material sandwiched between a reflective backplane comprising an array of addressable Field Effect Transistors (FETs), and one or more counter electrodes, thereby to define an array of addressable pixels, and the pulses are applied to one or more selected FETs and to the one or more counter electrodes thereby to drive selected pixels between an active state and the relaxed state. 13. A method according to claim 12 wherein data are applied to said bias pulses for driving the selected pixels to predetermined grey scale levels. 14. A method according to claim 12 or claim 13 wherein said selection pulses, bias pulses, erasure pulses and reset pulses are applied to selected FETs, and monopolar voltage first and second pulses are applied simultaneously to the counter electrode. 15. A method according to any one of claims 12 to 14 wherein the first pulse applied to the counter electrode has a pulse width that spans the combined pulse widths of the first selection pulse, the first bias pulse, the first erasure pulse, and the first reset pulse. 16. A method according to any one of claims 12 to 15 wherein the second pulse applied to the counter electrode has a pulse width that spans the combined pulse widths of the second selection pulse, the second bias pulse, the second erasure pulse and the reset pulse. 17. 17. A drive system for an antiferrolelectric liquid crystal display device that has an array of addressable pixels, each of which is defined between a pair of electrodes, the system comprising voltage generation means operable to apply the following sequence of monopolar voltage pulses to at least one of the pair of electrodes which define at least one selected pixel of the display device: (a) a first selection pulse operable to drive the selected pixel to a first activated state ; (b) a first bias pulse operable to cause the selected pixel to attain a predetermined grey scale level; (c) a first erasure pulse of opposite polarity to that of the first selection pulse operable to erase the memory of selected pixel and to switch the pixel to a relaxed inactive state : (d) a reset pulse operable to allow the pixel to reset in the relaxed state; (e) a second selection pulse of opposite polarity to that of the first selection pulse operable to switch the selected pixel to a second activated state; (f) a second bias pulse operable to cause the selected pixel to attain a predetermined grey scale level; (g) a second erasure pulse of opposite polarity to that of the second selection pulse operable to cause the selected pixel to switch to the relaxed inactive state and erase the memory of the pixel; and, (h) a reset pulse operable to allow the pixel to reset in the relaxed state. 18. A drive system according to claim 17 wherein the first and second bias pulse is of the same polarity as, but lower voltage than, respectively, the first and second selection pulses. 19. A drive system according to claim 17 or claim 18 wherein the first and second bias pulse is of the same polarity as, but higher voltage than, respectively, the first and second selection pulses 20. A drive system according to any one of the claims 17 to 19, wherein the reset pulses are at zero volts. 21. 21. A drive system according to any one of claims 17 to 20, wherein data for the selected pixel is incorporated with the first and second selection pulses. 22. A drive system according to any one of claims 17 to 21, wherein data for selected pixels are incorporated with the first and second bias pulses. 23. 23. A drive system according to any one of claims 17 to 22, wherein data for non-selected pixels are incorporated with the bias pulses. 24. 24. A drive system according to any one of claims 17 to 23, wherein data for non-selected pixels are incorporated with the reset pulses. 25. 25. A drive system according to any one of claims 17 to 24. wherein the display device is a passive matrix display device, and one of the electrodes of each pair of electrodes is constituted by one electrode of a first array of electrodes, and the other electrode of each pair is constituted either by an electrode common to all pairs of electrodes, or one electrode of a second array of electrodes, and the said pulses are applied sequentially to selected electrodes. 26. A drive system according to any one of claims 17 to 25, wherein a first electrode of the pair of electrodes is maintained at a predetermined datum voltage level relative to the second electrode of the respective pair of electrodes, and the selection pulses, bias pulses, and erasure pulses are applied to the second electrode of the pair of electrodes.. 27. A drive system according to any one of claims 17 to 26, wherein the selection pulses and the bias pulses are applied to a first electrode of the pair of electrodes. 28. A drive system according to any one of claims 17 to'5, wherein the display device comprises an antiferroelectric liquid crystal material sandwiched between a reflective backplane comprising an array of addressable Field Effect Transistors (FETs), and one or more counter electrodes, thereby to define an array of addressable pixels, and the pulses are applied to one or more selected FETs and to the one or more counter electrodes thereby to drive selected pixels between an active state and the relaxed state. 29. A drive system according to any one of claim 28, wherein data are applied to said bias pulses for driving the selected pixels to predetermined grey scale levels. 30. A drive system according to claim 28 or claim 29, wherein said selection pulses, bias pulses, erasure pulses and reset pulses are applied to selected FETs, and monopolar voltage first and second pulses are applied simultaneously to the counter electrode. 31. 31. A drive system according to any one of claims 28 to 30, wherein the first pulse applied to the counter electrode has a pulse width that spans the combined pulse widths of the first selection pulse, the first bias pulse, the first erasure pulse, and the first reset pulse. 32. A drive system according to any one of claims 28 to 31 wherein the second pulse applied to the counter electrode has a pulse width that spans the combined pulse widths of the second selection pulse, the second bias pulse, the second erasure pulse and the reset pulse. 33. 33. An antiferroelectric liquid crystal device that has an array of addressable pixels, each of which is defined between a pair of electrodes, the device including a drive system comprising a voltage generator means operable to applv the following sequence of monopolar voltage pulses to at least one of the pair of electrodes which define at least one selected pixel; (a) a first selection pulse operable to drive the selected pixel to a first activated state; (b) a first bias pulse operable to cause the selected pixel to attain a predetermined grey scale level ; (c) a first erasure pulse of opposite polarity to that of the first selection pulse operable to erase the memory of selected pixel and to switch the pixel to a relaxed inactive state; (d) a reset pulse operable to allow the pixel to reset in the relaxed state; (e) a second selection pulse of opposite polarity to that of the first selection pulse operable to switch the selected pixel to a second activated state; (f) a second bias pulse operable to cause the selected pixel to attain a predetermined grey scale level; (g) a second erasure pulse of opposite polarity to that of the second selection pulse operable to cause the selected pixel to switch to the relaxed inactive state and erase the memory of the pixel : and, (h) a reset pulse operable to allow the pixel to reset in the relaxed state. 34. 34. A liquid crystal device according to claim 33 wherein the first and second bias pulse is of the same polarity as, but lower voltage than, respectively, the first and second selection pulses. 35. 35. A liquid crystal device according to claim 33 wherein the first and second bias pulse is of the same polarity as, but higher voltage than, respectively, the first and second selection pulses 36. A liquid crystal device according to any one of claims 33 to 5. wherein the reset pulses are at zero volts. 37. A liquid crystal device according to any one of the claims 33 to 36, wherein data for the selected pixel is incorporated with the first and second selection pulses. 38. A liquid crystal device according to any one of claims 33 to 37, wherein data for selected pixels are incorporated with the first and second bias pulses. 39. 39. A liquid crystal device according to any of claims 33 to 38 wherein data for non-selected pixels are incorporated with the bias pulses. 40. A liquid crystal device according to any one of claims 33 to 39 wherein data for non selected pixels are incorporated with the reset pulses. 41. 41. A liquid crystal device according to any one of claims 33 to 40, wherein the display device is a passive matrix display device, and one of the electrodes of each pair of electrodes is constituted by one electrode of a first array of electrodes, and the other electrode of each pair is constituted either by an electrode common to all pairs of electrodes, or one electrode of a second array of electrodes, and the said pulses are applied sequentially to selected electrodes. 42. A liquid crystal device according to claim 41 wherein a first electrode of the pair of electrodes is maintained at a predetermined datum voltage level relative to the second electrode of the respective pair of electrodes, and the selection pulses, bias pulses, and erasure pulses are applied to the second electrode of the pair of electrodes.. 43. A liquid crystal device according to claim 41 or claim 42, wherein the selection pulses and the bias pulses are applied to a first electrode of the pair of electrodes. 44. A liquid crystal device according to any one of claims 33 to 40 wherein the display device comprises an antiferroelectric liquid crystal material sandwiched between a reflective backplane comprising an array of addressable Field Effect Transistors (FETs), and one or more counter electrodes, thereby to define an array of addressable pixels, and the pulses are applied to one or more selected FETs and to the one or more counter electrodes thereby to drive selected pixels between an active state and the relaxed state. 45. A liquid crystal device according to claim 44, wherein data are applied to said bias pulses for driving the selected pixels to predetermined grey scale levels. 46. A liquid crystal device according to claim 44 or claim 45, wherein said selection pulses, bias pulses, erasure pulses and reset pulses are applied to selected FETs, and monopolar voltage first and second pulses are applied simultaneously to the counter electrode. 47. A liquid crystal device according to any one of claims 44 to 45 wherein the first pulse applied to the counter electrode has a pulse width that spans the combined pulse widths of the first selection pulse, the first bias pulse, the first erasure pulse, and the first reset pulse. 48. A liquid crystal device according to any one of claims 44 to 47 wherein the second pulse applied to the counter electrode has a pulse width that spans the combined pulse widths of the second selection pulse, the second bias pulse, the second erasure pulse and the reset pulse.
