madrid2i

Resumen

A DRAM controller (103) may comprise two sub-controllers (406, 404), each capable of handling a respective N-bit interface (e.g. 64-bit interface). Each sub-controller may also be configurable to be (2*N)-bit (e.g. 128-bit) capable with respect to control logic, for controlling a logical 128-bit data path. In ganged mode, each sub-controller may logically operate as if it were handling data in 128-bit chunks, (i.e. handling the entire 128- bit data path), while actual full bandwidth may be achieved by having one of the sub-controllers operate on commands and a first N-bit portion of each (2*N)-bit chunk of data, and having the other sub-controller operate on a "copy" of the commands with a corresponding remaining N-bit portion of each (2*N)-bit chunk of data. Once the BIOS has configured and initialized the two DRAM controllers to operate in ganged mode, the BIOS and all software may no longer need to be aware that two memory controllers are used to access a single (2*N)-bit wide channel.

Reivindicaciones

We claim: 1. A method for accessing a memory channel having a (2*N)-bit data path, wherein N is a positive integer, the method comprising: transmitting access information to a first memory controller (406) having an N-bit data path, to transmit and/or receive (2*N)-bit chunks of data through the memory channel; copying the access information to a second memory controller (404) having an N-bit data path; in response to said transmitting the access information and said copying the access information: the first memory controller transmitting and/or receiving a first N-bit portion of each of the (2*N)-bit chunks of data over its N-bit data path; and the second memory controller transmitting and/or receiving a remaining N- bit portion of each of the (2*N)-bit chunks of data over its N-bit data path. 2. The method of claim 1, further comprising; the first memory controller transmitting and/or receiving the first N-bit portion of each of the (2*N)-bit chunks of data over its N-bit data path to and/or from a first physical memory (304) having N data lines coupled to the N-bit data path of first memory controller; and the second memory controller transmitting and/or receiving the remaining N-bit portion of each of the (2*N)-bit chunks of data over its N-bit data path to and/or from a second physical memory (302) having N data lines coupled to the N-bit data path of the second memory controller. 3. The method of claim 1, further comprising: prior to said transmitting the access information and said copying the access information, configuring the first memory controller and the second memory controller to operate in ganged mode; and executing firmware instructions to initialize a system comprising the first memory controller and the second memory controller; wherein said executing the firmware instructions comprises said configuring the first memory controller and the second memory controller. 4. The method of claim 1, wherein said transmitting access information to the first memory controller comprises transmitting address information; wherein the method further comprises: transmitting to the first memory controller one or more (2*N)-bit chunks of data corresponding to the address information, to store the one or more (2*N)-bit chunks of data according to the address information; and. replicating the one or more (2*N)-bit chunks of data corresponding to the address information to the second memory controller. 5. The method of claim 4, further comprising: the first memory controller transmitting a first N-bit portion of each of the one or more (2*N)-bit chunks of data corresponding to the address information over its N-bit data path to a first physical memory having N data lines coupled to the N-bit data path of first memory controller; and the second memory controller transmitting a remaining N-bit portion of each of the one or more (2*N)-bit chunks of data corresponding to the address information over its N- bit data path to a second physical memory having N data lines coupled to the N-bit data path of the second memory controller. 6. A memory system comprising: a first memory controller (103, 406) having an N-bit data path, wherein the first memory controller is configured to receive first type access information intended for transmitting and/or receiving corresponding (2*N)-bit chunks of data over a (2*N)-bit memory channel; a second memory controller (103, 404) having an N-bit data path; and a control block (410) coupled to the first memory controller and the second memory controller, and operable to replicate the first type access information received by the first memory controller over to the second memory controller; wherein the first memory controller is operable to transmit and/or receive a first N- bit portion of each of the (2*N)-bit chunks of data over its N-bit data path according to the received first type access information, and the second memory controller is operable to transmit and/or receive a remaining N-bit portion of each of the (2*N)-bit chunks of data over its N-bit data path according to the replicated first type access information. 7. The memory system of claim 6; wherein the first memory controller and the second memory controller are further configured to each receive respective second type access information intended for transmitting and/or receiving respective N-bit chunks of data over respective N-bit memory channels; wherein the first memory controller is operable to transmit and/or receive its respective N-bit chunks of data over its N-bit data path according to its received respective second type access information, and the second memory controller is operable to transmit and/or receive its respective N-bit chunks of data over its N-bit data path according to its received second type access information. 8. The memory system of claim 6, further comprising: a first memory module (304) having N data lines coupled to the N-bit data path of the first memory controller; and a second memory module (302) having N data lines coupled to the N-bit data path of the second memory controller; wherein the first memory controller is operable to transmit and/or receive a first N- bit portion of each of the (2*N)-bit chunks of data to and/or from the first memory module over its N-bit data path; and wherein the second memory controller is operable to transmit and/or receive a remaining N-bit portion of each of the (2*N)-bit chunks of data to and/or from the second memory module over its N-bit data path. 9. The memory system of claim 6, wherein the first memory controller and the second memory controller are operable to operate as one of: a single (2*N)-bit wide dual-channel memory controller; or two N-bit wide single-channel memory controllers. 10. A system (100) comprising the memory system recited in any of claims 6 to 9, and further comprising a processing unit (101) configured to execute instructions to configure the first memory controller and the second memory controller through the control block.

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