madrid2i

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An integrated power device module having a leadframe structure with first and second spaced pads and one or more common source-drain leads located between said first and second pads, first and second transistors flip chip attached respectively to said first and second pads, wherein the source of said second transistor is electrically connected to said one or more common source-drain leads, and a first clip attached to the drain of said first transistor and electrically connected to said one or more common source-drain leads. In another embodiment a partially encapsulated power quad flat no-lead package having an exposed top thermal drain clip which is substantially perpendicular to said with a folded stud exposed top thermal drain clip, and an exposed thermal source pad.

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CLAIMS 1. An integrated power device module comprising: a leadframe structure having first and second spaced pads and one or more common source-drain leads located between said first and second pads; first and second transistors flip chip attached respectively to said first and second pads, wherein the source of said second transistor is electrically connected to said one or more common source-drain leads; and a first clip attached to the drain of said first transistor and electrically connected to said one or more common source-drain leads. 2. The module of claim 1 wherein said first and second transistors are metal oxide semiconductor field effect transistors (MOSFET). 3. The module of claim 1 wherein said first and second transistors are respectively high side and low side power transistors that are components of a buck converter. 4. The module of claim 1 wherein said leadframe structure includes one or more drain leads located on the outside of said second pad, and including a second clip attached to the drain of said second transistor and electrically connected to said one or more drain leads located on the outside of said second pad. 5. The module of claim 1 wherein said leadframe structure, said transistors and said clip are encapsulated in molding material, with the pads of the leadframe structure and the clip being exposed to provide dual-sided cooling of said module. 6. An integrated power device module comprising: a leadframe structure having first and second spaced pads, one or more common source-drain leads located between said first and second pads, and one or more drain leads located on the outside of said second pad; first and second transistors flip chip attached respectively to said first and second pads, wherein the source of said second transistor is electrically connected to said one or more common source-drain leads; a first clip attached to the drain of said first transistor and electrically connected to said one or more common source-drain leads; a second clip attached to the drain of said second transistor and electrically connected to said one or more drain leads located on the outside of said second pad; and molding material encapsulating said leadframe structure, said transistors, and said clips to form said module. 7. The module of claim 6 wherein said pads of the leadframe structure and the clips are exposed and free from molding material to provide dual-sided cooling of said module. 8. The module of claim 6 wherein said first and second transistors are metal oxide semiconductor field effect transistors (MOSFET). 9. The module of claim 6 wherein said first and second transistors are respectively high side and low side power transistors that are components of a buck converter. 10 The module of claim 6 wherein said one or more common source-drain leads are configured to be cut so that two individual single transistor packages can be formed. 1 1. The module of claim 6 wherein said leadframe structure has a gate lead between said first and second pads and wherein said first clip is not electrically attached to said gate lead. 12. The module of claim 6 wherein said first clip has a planar member and downwardly extending leads that are electrically connected to said common source- drain leads of said leadframe structure; and wherein said second clip has a planar member and downwardly extending leads that are electrically connected to said one or more drain leads of said leadframe structure located on the outside of said second pad. 13. The module of claim 12 wherein said leadframe structure has a gate lead between said first and second pads and wherein said first clip has no downwardly extending lead to be electrically connected to said gate lead. 14. The module of claim 6 wherein said leadframe structure is configured to have a leaded footprint which can be converted to a leadless module by cutting off the lead portion of the module. 15. The module of claim 6 wherein said common source drain leads are partially severed to disconnect the connection, and wherein a common heat sink is attached to and connects said first and second clips. !6. The module of claim 6 including an integrated circuit attached to said leadframe structure and electrically connected to said first and second transistors, said integrated circuit being encapsulated by said molding material to form a single module. 17. A method of making an integrated power device module comprising the steps of: providing a leadframe structure having first and second spaced pads, one or more common source-drain leads located between said pads and one or more drain leads located on the outside of said second pad; flip chip attaching first and second transistors respectively to said first and second pads, wherein the source of said second transistor is electrically connected to said one or more common source-drain leads; attaching a first clip to the drain of said first transistor and electrically connecting said first clip to said one or more common source-drain leads; attaching a second clip to the drain of said second transistor and electrically connecting said second clip to said one or more drain leads located on the outside of said second pad; and encapsulating said leadframe structure, said transistors, and said clips with molding material to form said module. 18 The method of claim 17 wherein said pads of the leadframe structure and said clips are exposed and free from molding material to provide dual-sided cooling of said module. 19. The method of claim 17 wherein said first and second transistors are metal oxide semiconductor field effect transistors (MOSFET). 20. The method of claim 17 wherein said first and second transistors are respectively high side and low side power transistors that are components of a buck converter. 21. A partially encapsulated semiconductor package having an exposed top thermal clip with a plurality of folded bent portions which are substantially perpendicular to said exposed top portion of said thermal clip, and an exposed thermal leadframe structure pad. 22. The package of claim 21 wherein said top thermal clip has one or more cutouts on one or more top side edges which are filed in with encapsulating material. 23. The package of claim 21 further including a semiconductor device attached to said clip and to a leadframe structure having three separate segments which are coplanar. 24. A method of making a partially encapsulated semiconductor package comprising the steps of: providing a coplanar leadframe structure having three separate segments, a control segment, a first high current segment and a second high current segment; attaching a semiconductor device to two of said control segment and said first current segment; attaching a clip to a side of said semiconductor device opposite said leadframe structure which has a plurality of bent portions, said plurality of bent portions being attached to said second current segment; and partially encapsulating said leadframe structure, said semiconductor device, and said clip with molding material to form said package.

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