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MEMORY DIAGNOSTICS SYSTEM AND METHOD WITH HARDWARE-BASED READ/WRITE PATTERNSCM Patents

A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output.

Datos clave

CategoríaInvención

Índice de la ficha

Updated at
05/11/2026
Numero publicacion
US.2012159271.A1
Fecha publicacion
21/06/2012
Anio publicacion
2012
Numero solicitud
US20100972977

Etiquetas

Inventores
Cho HanwooAskar TahsinMadrid Philip E.Madrid Philip eKrishnan GuhanAmick Brian W.Amick Brian WSearles ShawnHensley Ryan JHensley Ryan J.
Solicitantes
Advanced Micro Devices Inc.
Clasificacion ipc
G06F 11/ 00 A IG06F 11/ 263 A I
Clasificacion cpc
714/716714/717714/E11.177
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