Reivindicaciones
What is claimed is: 1. A packaged system for integrated circuits, semiconductor devices and passive components comprising: a molding compound encasing: an interconnect substrate with an upper surface that has a plurality of upper contacts arranged in a ring about a central region; a lower surface that has a plurality of lower contacts dispersed within a region bound by the ring; a plurality of interconnects, each of the interconnects connecting an upper contact to a lower contact, the interconnects being embedded in an insulator for electrically isolating the interconnects from one another; at least one integrated circuit mounted on the central region of the upper surface and electrically connected to the plurality of upper contacts; a molded trace frame with a bottom surface and a top surface, and having a plurality of traces encased in the molding compound such that a surface of the trace is exposed outside of the molding compound and the top surface includes a plurality of trace contacts that are in electrical communication with the plurality of lower contacts. 2. The package of systems as recited in claim 1, wherein the lower contacts are arranged in a grid. 3. The package of systems as recited in claim 1, further comprising a ball grid array electrically connected to the bottom surface of the trace. 4. The package of systems as recited in claim 1, wherein the integrated circuit is electrically connected to the plurality of upper contacts by wirebonds. 5. The package of systems as recited in claim 1, further comprising a second integrated circuit which contacts the top surface of the conductive trace thus forming an electrical contact between the second integrated circuit and the trace. 6. The package of systems as recited in claim 1, wherein the trace includes a plurality of leads configured such that those leads that connect to the integrated circuit extend to either a first edge or a second edge of the molding compound, wherein the first edge and second edge are adjacent to one another. 7. The package of systems as recited in claim 6, wherein at least one of the leads that connects to the integrated circuit runs under the integrated circuit. 8. The package of systems as recited in claim 1, wherein the integrated circuit is mounted in a corner. 9. The package of systems as recited in claim 1, the trace is encased within the molding compound such that a lateral surface of the trace is exposed on the side of the molding compound. 10. The package of systems as recited in claim 1, wherein the at least one integrated circuit includes at least three integrated circuits. 11. The package of systems as recited in claim 1, wherein the at least one integrated circuit includes a second integrated circuit that is electrically connected to the trace with a folded clip. 12. The package of systems as recited in claim 11, wherein the second integrated circuit is a MOSFET. 13. The package of systems as recited in claim 12, wherein the MOSFET has a drain connected to the trace through the folded clip. 14. The package of systems as recited in claim 11, wherein a surface of the folded clip extends outside of the molding compound. 15. The package of systems as recited in claim 11, wherein the folded clip is entirely encased within the molding compound. 16. The package of systems as recited in claim 1, further comprising one or more devices selected from the group consisting of logic integrated circuits, DRAMS, SRAMS, programmable logic devices, flash memory devices, diodes, MOSFETS, IGBTs, and thyristors, capacitors, inductors and resistors. 17. A packaged system for integrated circuits, semiconductor devices and passive components comprising: a molding compound encasing: a interconnect substrate with an upper surface that has a plurality of upper contacts arranged in a ring about a central region; a lower surface that has a plurality of lower contacts dispersed within a region bound by the ring; a plurality of interconnects, each of the interconnects connecting an upper contact to a lower contact, the interconnects being embedded in an insulator for electrically isolating the interconnects from one another; a plurality of integrated circuits including a first integrated circuit mounted on the central region of the upper surface and electrically connected to the plurality of upper contacts and a second integrated circuit wherein the first and second integrated circuits are independently selected from the group consisting of a logic integrated circuit, a DRAM device, a SRAM device, a programmable logic device, a flash memory device, diodes, a MOSFET, a IGBT, a thyristor, a capacitor, an inductor and a resistor; a molded trace frame with a bottom surface and a top surface, and having a plurality of traces being encased such that the bottom surface is exposed outside of the molding compound and the top surface includes a plurality of trace contacts that are in electrical communication with the plurality of lower contacts, the MOSFET being electrically connected to the trace frame such that the gate, the source, and the drain are all electrically connected to the bottom surface. 18. A method for packing a microelectronic system with a plurality of components comprising the steps of encasing a molded trace frame with a bottom surface, a top surface, and a plurality of traces in a first molding compound such that the bottom surface is exposed outside of the molding compound and the top surface includes a plurality of trace contacts; attaching an interconnect substrate to the trace frame, the interconnect substrate having: an upper surface that has a plurality of upper contacts arranged in a ring about a central region; a lower surface that has a plurality of lower contacts dispersed within a region bound by the ring; a plurality of interconnects, each of the interconnects connecting an upper contact to a lower contact, the interconnects being embedded in an insulator for electrically isolating the interconnects from one another; the interconnect substrate being attached such that the trace contacts are in electrical communication with the plurality of lower contacts; mounting a plurality of integrated circuits including a first integrated circuit mounted on the central region of the upper surface; and electrically connecting the first integrated circuit to the plurality of upper contacts. 19. The method as recited in claim 18, further comprising the step of encasing the package in a second molding compound such that a surface of the trace remains frame exposed, and the interconnect substrate and the plurality of integrated circuits are enclosed.
