The present invention relates to a method for producing three-dimensional semiconductor nanoparticles from self-assembled metal nanoparticles. The method combines the deposition of a metal onto a semiconductor substrate using physical deposition techniques with reactive ion plasma etching of the metal-semiconductor assembly. The method is simple, rapid, and inexpensive, and obviates the need for lithographic processes. (Machine-translation by Google Translate, not legally binding)
1. CLAIMS 2. 1. A process for producing three-dimensional semiconductor nanoparticles, comprising the following steps: 3. a) providing a substrate comprising a semiconductor material; b) depositing a metal with a sufficiently low surface tension to form self-assembled metallic nanoparticles when said metal is deposited onto the substrate by physical deposition techniques, obtaining a substrate at least partially coated with self-assembled metallic nanoparticles; and 4. c) attack the substrate coated at least partially with metallic nanoparticles using Reactive Ion Etching (RIE) techniques, obtaining three-dimensional semiconductor nanoparticles deposited on the substrate. 5. 2. The process of claim 1, wherein the semiconductor material of the substrate in step a) is GaAs. 6. 3. The process of claim 1 or 2, wherein the metal in step b) is selected from gallium, indium and bismuth, alone or in any combination thereof. 7. 4. The process of any of claims 1 to 3 above, wherein the physical deposition technique used in step b) is selected from thermal evaporation techniques, either by Joule effect or with electron gun, Metal-Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE). 8. 5. The process of claim 4, wherein the physical deposition technique is thermal evaporation by Joule effect. 9. 6. The process of claim 5 wherein Ga is used as a semiconductor metal and GaAs as a substrate, and the deposition is carried out in a vacuum chamber at a pressure of 1.5-10'<5>mbar, applying 50 W to a tungsten filament, which causes the evaporation of the Ga, which is then deposited onto the GaAs substrate. 10. 7. The process of claim 6 wherein, after step b), when the self-assembled metallic nanoparticles are exposed to air, a 2-3 nanometer amorphous Ga oxide (GaxOy) crust is formed on them. 11. 8. The process of any of the preceding claims, wherein the self-assembled metallic nanoparticles cover between 40% and 50% of the substrate surface. 12. 9. The process of any of the preceding claims, wherein the Reactive Ion Etching (RIE) technique of step c) is Inductively Coupled Plasma Reactive Ion Etching (RIE-ICP). 13. 10. The process of claim 9, wherein the reactive ion plasma is a plasma of noble gases, diatomic molecules, hydrocarbons, chlorinated and/or fluorinated compounds, or a combination thereof. 14. 11. The process of claim 10, wherein the reactive ion plasma is an Ar plasma. 15. 12. The process of any of claims 9-11 above, wherein the ICP-RIE reactive ion plasma attacks both the self-assembled metallic nanoparticles and the uncoated semiconductor substrate between nanoparticles. 16. 13. The process of any of claims 9-12 above, wherein the ICP-RIE etching is carried out under an Ar flow of 30 cm⁻² standard per minute, at a pressure of 66.66 mbar, applying a radio frequency power of 220 W and an ICP power of 100 W. 14. The process of any of claims 9-13 above, wherein both the shape of the resulting semiconductor nanoparticles and the percentage of substrate coverage thereof are regulated by modifying the parameters of the ICP-RIE etching, such as the ICP and/or RF power, the pressure in the chamber, or the introduced gas flow rate. 17. 15. The process of any of the preceding claims, wherein the size of the resulting semiconductor nanoparticles is regulated by adjusting the amount of metal that is evaporated. 18. 16. Self-assembled metallic nanoparticles obtained from step b) of the procedure of any of claims 1 to 15 above. 19. 17. Self-assembled metallic nanoparticles according to claim 16, having a height/width aspect ratio of approximately 0.44. 20. 18. Self-assembled metallic nanoparticles according to claim 16 or 17, which are hemispherical and have a radius between 10 and 500 nm. 21. 19. Three-dimensional semiconductor nanoparticles obtained according to the procedure of any of claims 1 to 15 above. 22. 20. Three-dimensional semiconductor nanoparticles according to claim 19, having an approximately conical shape. 23. 21. Three-dimensional semiconductor nanoparticles according to claims 19 or 20, having a size between 10 and 500 nm. 24. 22. Three-dimensional semiconductor nanoparticles according to any of claims 19 to 21 having a height/width aspect ratio of 0.77 and a radius less than 30 nm.