madrid2i

Resumen

A folded frame carrier has a die attach pad (DAP) (30) and one or more folded edges (32, 33, 34, 35). Each folded edge has one or more studs (36) and each stud has a trapezoidal tip. The folded frame carrier may be made of single gauge copper or copper alloy. Multiple folded frame carriers may be formed between opposite rails of a lead frame. The folded edges are cut with a relief groove. The tips are formed in edges of the DAP and then the tips are folded upright. The tips provide electrical connection to the terminal on the rear surface of a power semiconductor mounted on the DAP.

Reivindicaciones

CLAIMS 1. A method for packaging a semiconductor die comprising the steps of: providing a lead frame with a planar portion for receiving and holding the semiconductor die; forming one or more studs along one edge of the planar portion of the lead frame; forming a groove in the surface of the planar portion disposed parallel to the edge with studs and spaced from the studs; bending the edge with studs around the groove to an angle with respect to the planar portion of the lead frame. 2. The method of claim 1 wherein the angle is between 84 and 90 degrees. 3. The method of claim 1 wherein the step of forming one or more studs comprises removing material from the edge to leave one or studs of material along said edge. 4. The method of claim 3 comprising the further step of tapering the surfaces of the tip(s) of the stud(s). 5. The method of claim 4 comprising the further step of spanking the end of the stud to form a tip with a trapezoid-shaped tip. 6. The method of claim 1 wherein the step of forming a groove includes machining a v-groove into the surface of the planar portion of the lead frame. 7. The method of claim 1 further comprising providing a semiconductor die with a die attach surface and a ball grid array surface, attaching the die attach surface of the semiconductor die to the planar portion of the lead frame so that the ball grid array faces away from the planar portion of the lead frame, and bending the edge about an axis parallel to the groove until the ends of the studs are coplanar with the array of balls disposed on the surface of the semiconductor die. 8. The method of claim 1 comprising the further steps of: providing a semiconductor die with only one terminal on one surface and one or more terminals on its other surface; forming a planar contact on surface with only one terminal and forming a ball grid array of contacts on other surface; attaching the planar contact surface of the semiconductor die to the planar portion of the lead frame; bending the edge with studs about an axis parallel to the groove until the ends of the studs are coplanar with the ball grid array. 9. The method of claim 8 wherein the semiconductor is a mosfet and the surface with only one terminal carries a drain terminal the other surface carries source and gate terminals. 10. The method of claim 8 further comprising the steps of attaching the semiconductor die to a printed circuit board. 11. The method of claim 1 further comprising: forming one or more studs along a second edge of the planar portion of the lead frame; forming a second groove in the surface of the planar portion disposed parallel to the second edge with studs and spaced from the studs; bending the second edge with studs to an angle with respect to the planar portion of the lead frame. 12. The method of claim 10 further comprising: forming one or more studs along a third edge of the planar portion of the lead frame; forming a third groove in the surface of the planar portion disposed parallel to the second edge with studs and spaced from the studs; bending the third edge with studs to an angle with respect to the planar portion of the lead frame. 13. A flip chip packaged semiconductor device comprising: a die attach pad comprising a planar portion for receiving a semiconductor die; an adhesive or solder layer on the planar portion for holding a semiconductor die; a semiconductor die having one surface facing and attached to the planar portion of the die attach pad by adhesive or solder; a wall along one edge of the die attach pad and disposed transverse to the die attach pad; and a plurality of studs extending from the wall and spaced from each other. 14. The flip chip packaged semiconductor device of claim 13 wherein the semiconductor further comprises an array of bumps or balls on a surface opposite the surface facing the planar portion of the die attach pad. 15. The flip chip package of claim 13 wherein the tip of the studs and the tips of the bumps or balls lie in a common plane. 16. The flip chip package of claim 13 wherein the studs have tapered tips. 17. The flip chip package of claim 13 wherein the tips have a trapezoidal taper. 18. The flip chip package of claim 13 wherein the die attach pad and walls are formed from a sheet of copper or copper alloy. 19. A flip chip packaged semiconductor device comprising: a die attach pad comprising a planar portion for receiving a semiconductor die and by one or more edges; an adhesive or solder layer on the planar portion for holding a semiconductor die; a semiconductor die having one surface facing and attached to the planar portion of the die attach pad by adhesive or solder and another surface with bump or ball contacts; one or more walls, each wall along an edge of the die attach pad and disposed transverse to the die attach pad; and a plurality of studs extending from each wall and spaced from each other. 20. The flip chip packaged semiconductor of claim 19 wherein the die attach pad has four edges and at least one wall with studs. 21. The flip chip packaged semiconductor of claim 19 wherein the die attach pad has four edges and at least two walls with studs. 22. The flip chip packaged semiconductor of claim 19 wherein the die attach pad has four edges and at least three walls with studs. 23. The flip chip packaged semiconductor of claim 19 wherein the studs are substantially coplanar with the bump or ball contacts. 24. The flip chip packaged semiconductor of claim 19 wherein ajunction of the base of the walls and the die attach pad is defined by a groove of removed die attach material. 25. The flip chip packaged semiconductor of claim 19 wherein the wall is bent about an axis defined by the groove. 26. The flip chip packaged semiconductor of claim 19 wherein the die attach pad and the walls comprises a common material and the junction of the base of the walls and the die attach pad is further defined by a bend in said material. 27. A method for packaging a semiconductor die comprising the steps of: providing a lead frame with a planar die attach pad for receiving and holding the semiconductor die; punching studs into one or more edges of the die attach pad to form one or more studs projecting from each punched edge; cutting a groove in the surface of the die attach pad proximate to each punched edge; bending each punched edge about its respective cut groove in a direction toward the groove to dispose the punched edge with studs at an angle with respect to the die attach pad. 28. The method of claim 27 further comprising the steps of: providing a semiconductor die with one surface planar with a planar contact and an opposite surface with bump contacts; attaching the planar surface of the semiconductor die to the planar die attach pad; bending each punched edge with studs about an axis parallel to its respective groove until the ends of the studs are coplanar with the tip of the bumps of the semiconductor surface.

Índice de la ficha

En detalle

Resumen

Reivindicaciones

Etiquetas