Reivindicaciones
1. A method for the selective tracing of program instructions which, given a program for which pre-processed source files (4), object files with debugging information (5), and a symbol localisation file (6) generated during the linking (7) are provided, comprises the following steps (1, 2, 3): 1. selecting the statements to be traced on the pre-processed source files of the program (4), the elements that characterize each statement being: the name of the source file (15), the line number (8) of the statement within that file, and the type of trace (9); basic if it only traces the time of execution of the statement, or non-basic if it also traces the value of some element of the internal state of the processor, which is intended to be performed; 2. automatically identifying, for each statement (10) selected, the relative address (14) of the instruction to be traced (11) that completes the execution of said statement, using the object files with program debugging information (5); 3. automatically obtaining the content of an auxiliary memory (12), comprising trace codes (17) and no-operation codes (18), using the elements that characterize each statement (10) selected, the relative address (14) identified within the object file of the instruction to be traced that corresponds to the statement (10) selected, and the information from the symbol localisation file (6) obtained during the linking (7) of the object files of the program (5) that generates the executable file (13); in order to obtain, for each statement (10) selected, the trace code (17) and its displacement within the auxiliary memory storing the same, the trace codes (17) being aligned with the instructions to be traced (11) in the content of the program memory (13); where aligned means that the displacement (16) of each trace code (17) within the content of the auxiliary memory (12) is the same as that of the instruction to be traced (11) within the content of the program memory (13), and those positions of the auxiliary memory that have the same displacement as the program instructions that have not been selected for tracing are completed with NOP no-operation codes (18). 2. - A processing device capable of performing parallel searching, decoding and execution of program instructions and trace codes obtained on the basis of the method of claim 1, comprising two "TRACE" and "NOMINAL" working modes, characterized in that it comprises: • a search step (100), which in turn comprises: ∘ an instruction address calculation module (109), ∘ a main search module (103), capable of simultaneously reading an instruction (104) in the program memory (101) and a code (105) in an auxiliary memory (102), • a decoding step (114) which in turn comprises: ∘ a program instruction decoding module (115), ∘ a trace instruction decoding module (116), • a program instruction pipeline (132), • a trace instruction pipeline (133), • an output register (134) that receives the trace information obtained upon execution of a trace instruction, • a data path comprising an array of multiplexers (110,124,137,138,139), • a data path controller, having an array of inputs (120), formed by the signals (107, 108, 135, 143, 144, 145, 146) calculated in the different steps, and generating an array of outputs (121), which control the multiplexers (110,124,137,138,139) and the loading in the registers associated with the different steps (111, 115, 126, 127, 128, 129, 130, 131), as well as the loading of the trace information obtained after the execution of a trace instruction in the output register (134), 3. - The processing device as claimed in claim 2, where in the "NOMINAL" type working mode, the search step (100) simultaneously reads a program instruction (104) from the program memory (101) and a code (105) from the auxiliary memory (102), and interprets said code (105) in the main module of the search step (103) as an error detection and correction code; so that the instruction (104) read from the program memory (101) can be corrected, in the event of a recoverable error, and is supplied error-free to the program instruction decoder (115) of the decoding step (114) in a subsequent cycle as a valid program instruction (117) and, in the event that the error is not recoverable, the main module (103) of the search step (100) activates a signal (108) that is interpreted by the processor as an exception. 4. - The processing device as claimed in claim 2, where, in the "TRACE" type working mode, the search step (100) simultaneously reads a program instruction (104) from the program memory (101) and a code (105) from the auxiliary memory (102), and performs in the main module (103) of the search step (100) the combination of the code (105) read from the auxiliary memory (102) with the address (106) corresponding to the program instruction (104) read from the program memory (101), in order to construct a trace instruction (118) that in the following cycles is decoded and executed in parallel and synchronously with the program instruction (117), employing a trace instruction pipeline (133) that generates, as a result of the execution, a result value (TR, 147) that will be stored in the final step (TE5) of the trace instruction pipeline (133); and employs the trace instruction decoding module (116), present in the decoding step (114), which supplies the trace instruction pipeline 133. 5. - The processing device as claimed in claim 4, where the data path controller (119), in the event that the trace instruction decoder (116) detects a no-operation code "NOP" in the trace instruction (118), establishes the data path of the trace instruction pipeline (133) so that its "TE3" step (127) receives a 0 and does not load a valid trace instruction, setting a value of 1 in the "SEL_TE3" signal (140) that controls the multiplexer (137). 6. - The processing device as claimed in claim 5, where the trace instruction pipeline (133) stores in its final "TE5" step (131) the trace information obtained after the execution of a trace instruction (116), this information being formed by the address of the program instruction "DIRI" (149), which is executed in parallel, and the data obtained after the execution of the trace instruction "TR" (147); and in the event that a valid trace instruction has not been executed in parallel with the program instruction, the value of the "DIRI" field (149) stored in "TE5" (131) is equal to 0. 7. - The processing device as claimed in claim 6, where the trace instruction pipeline (133), loads that information in the output register (134) provided that the "DIRI" field (149) stored in "TE5" (131) is different from 0, in accordance with the value of the "TE_DlRl_ES_0" signal (135). 8. - The processing device as claimed in claim 7, where the data path controller (119), in the event of detecting the activation of the "BUBBLE_E2" signal (143), which corresponds to the insertion of a bubble into the program instruction decoding module (115), sets the "SEL_TE2" selection signal of the multiplexer (124) inputting to the decoding module of the trace instruction (116) at 1, and thus, parallel to the bubble inserted in the program instruction decoding module (115), a non-operating trace instruction is loaded into the trace instruction decoding module (116). 9. - The processing device as claimed in claim 8, where, with the processing device in TRACE mode and in the event of detecting the activation of the "BUBBLE_E3" signal (144), corresponding to the insertion of a bubble in step 3, "E3" (126) of the program instruction pipeline (132), the data path controller (119) sets the "SEL_TE3" selection signal (140) of the multiplexer (137) inputting to step 3, "TE3" (127), of the trace instruction pipeline (133) at 1; and thus, and parallel to the bubble inserted in step 3, "E3" (126) of the program instruction pipeline (132), a non-operating trace instruction is loaded in step 3, "TE3" (127) of the trace instruction pipeline (133); 10. - The processing device as claimed in claim 9, where, with the processing device in TRACE mode and in the event of detecting the activation of the "BUBBLE_E4" signal (145) corresponding to the insertion of a bubble in step 4, "E4" (128), of the program instruction pipeline (132), the data path controller (119) sets the "SEL_TE4" selection signal (141) of the multiplexer (138) inputting to step 4, "TE4" (129), of the trace instruction pipeline (133) at 1; and thus, parallel to the bubble inserted in stage 4, "E4" (128) of the program instruction pipeline (132), a non-operating trace instruction is loaded in stage 4, "TE4" (129) of the trace instruction pipeline (133); 11. - The processing device as claimed in claim 10, where, with the processing device in TRACE mode and in the event of detecting the activation of the "BUBBLE_E5" signal (146) corresponding to the insertion of a bubble in step 5, "E5" (130) of the program instruction pipeline (132), the data path controller (119) sets the "SEL_TE5" selection signal (142) of the multiplexer (139) inputting to step 5, "TE5" (131) of the trace instruction pipeline (133) at 1; and thus, parallel to the bubble inserted in step 5, "E5" (130) of the program instruction pipeline (132), a non-operating trace instruction is loaded in stage 5, "TE5" (131) of the trace instruction pipeline (133). 12. - A processor characterised in that it comprises a processing device capable of working in two modes, which we call "TRACE" mode and "NOMINAL" mode, as claimed in any of the preceding claims, where in "NOMINAL" mode it uses an auxiliary memory, whose words are read in parallel with the program instructions, and are used as program instruction error detection and correction codes. where in "TRACE" mode that same auxiliary memory is used to store codes that enable the tracing of the program instructions, and that are read and executed in parallel with the program instructions, as claimed in any of the preceding claims.
